Title :
An efficient component (IN-RAM) for buffer management and multi-protocol implementation in ATM systems
Author :
Doumenis, G. ; Konstantoulakis, G. ; Korinthios, G. ; Lykakis, G. ; Reisis, D. ; Synnefakis, George
Author_Institution :
Div. of Comput. Sci., Nat. Tech. Univ. of Athens, Greece
Abstract :
This paper presents an intelligent shared buffer architecture specifically designed to facilitate emerging networking applications. The work conducted during the design of the IN-RAM component has produced a VLSI component architecture, suitable for high speed packet networks. The IN-RAM has built-in modules to control and monitor data buffering per connection basis or per destination basis, performing at the same time essential protocol operations. The architecture embeds both the processing and the memory modules, thus producing a true “system on a chip” solution
Keywords :
VLSI; application specific integrated circuits; asynchronous transfer mode; broadband networks; buffer storage; data communication equipment; microprocessor chips; packet switching; protocols; random-access storage; shared memory systems; telecommunication computing; telecommunication control; telecommunication network management; ATM systems; IN-RAM component; VLSI component architecture; buffer management; built-in modules; high speed packet networks; intelligent shared buffer architecture; internal DRAM; memory modules; multi-protocol implementation; networking applications; processing modules; protocol operations; system-on-a-chip; Communication system control; Cost function; Design optimization; Intelligent networks; Memory management; Physics; Random access memory; Scheduling; System performance; Very large scale integration;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.812231
