A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM

Author

von Arnim, K. ; Augendre, E. ; Pacha, C. ; Schulz, T. ; San, K.T. ; Bauer, F. ; Nackaerts, A. ; Rooyackers, R. ; Vandeweyer, T. ; Degroote, B. ; Collaert, N. ; Dixit, A. ; Singanamalla, R. ; Xiong, W. ; Marshall, A. ; Cleavelin, C.R. ; Schrüfer, K. ; Jurc

Author_Institution

Infineon Technol., Leuven

fYear

2007

fDate

12-14 June 2007

Firstpage

106

Lastpage

107

Abstract

This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undopedfins show an inverter delay of 13.9ps at 1V, the highest performance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS. SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration.

Keywords

CMOS integrated circuits; SRAM chips; invertors; large scale integration; low-power electronics; FET CMOS technology; SRAM cells; current 1.9 nA; digital performance; high performance digital circuits; inverter delay; large scale integration; low power; metal gates; multi gate; ring oscillators; time 13.9 ps; undopedfins; voltage 1 V; CMOS digital integrated circuits; CMOS technology; Delay; Digital circuits; FETs; Integrated circuit technology; Inverters; Large scale integration; Performance analysis; Random access memory;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-03-1

Type

conf

DOI

10.1109/VLSIT.2007.4339745

Filename

4339745