Title :
Technology Breakthrough of Low Temperature, Low Defect, and Low Cost SiGe Selective Epitaxial Growth (L3 SiGe SEG) Process for 45nm Node and Beyond
Author :
Shimamune, Y. ; Fukuda, M. ; Koiizuka, M. ; Katakami, A. ; Hatada, A. ; Ikeda, K. ; Kim, Y. ; Kawamura, K. ; Tamura, N. ; Mori, T. ; Moriya, A. ; Hashiba, Y. ; Inokuchi, Y. ; Kunii, Y. ; Kase, M.
Author_Institution :
Fujitsu Lab. Ltd., Tokyo
Abstract :
We have developed low temperature, low defect and low cost SiGe selective epitaxial growth (L3 SiGe SEG) process using a high throughput batch type CVD process at first time. Defect is eliminated by low temperature pre-cleaning and recess shape control. As a result, we have achieved the high quality SiGe SEG, improving the compressive channel stress and reducing the junction leakage. We also improved the NMOS short channel effects by low temperature SiGe SEG. Finally, in combination of low temperature SiGe SEG, dual stress SiN liner, and low thermal budget metallization, drive current of 725 muA/mum in PMOS and 940 muA/mum in NMOS were achieved at off current (Ioff) =100 nA/mum at drain bias (VDD) = 1.0 V.
Keywords :
CVD coatings; Ge-Si alloys; MIS devices; chemical vapour deposition; semiconductor device metallisation; semiconductor epitaxial layers; semiconductor growth; semiconductor materials; vapour phase epitaxial growth; NMOS; NMOS short channel effects; PMOS; SiGe; compressive channel stress; defect elimination; high throughput batch type CVD process; junction leakage reduction; low temperature precleaning; low thermal budget metallization; recess shape control; selective epitaxial growth; Compressive stress; Costs; Epitaxial growth; Germanium silicon alloys; MOS devices; Shape control; Silicon germanium; Temperature; Thermal stresses; Throughput;
Conference_Titel :
VLSI Technology, 2007 IEEE Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-4-900784-03-1
DOI :
10.1109/VLSIT.2007.4339749
