Stress dependence and poly-pitch scaling characteristics of (110) PMOS drive current

Author

Yang, B. Frank ; Nummy, K. ; Waite, A. ; Black, L. ; Gossmann, H. ; Yin, H. ; Liu, Y. ; Kim, B. ; Narasimha, S. ; Fisher, P. ; Meer, H.V. ; Johnson, J. ; Chidambarrao, D. ; Kim, S.D. ; Sheraw, C. ; Wehella-gamage, D. ; Holt, J. ; Chen, X. ; Park, D. ; Sun

Author_Institution

Adv. Micro Devices, Hopewell Junction

fYear

2007

fDate

12-14 June 2007

Firstpage

126

Lastpage

127

Abstract

This work demonstrates that the ~2times mobility advantage of (110) PMOS over (100) PMOS is maintained down to 190 nm liners poly-pitch for devices under compressive stress. (110) PMOS with 3.5 GPa compressively stressed liners demonstrate strong channel drives with I_on=800 muA/mum at I_off=100 nA/mum (V_dd=10 V) for 190 nm poly-pitch, the highest reported to date for 45-nm-node (110) PMOS using conventional gate dielectrics without eSiGe stressors. Additionally, (110) PMOS show better scalability, with 15% smaller total I_on degradation than (100) PMOS when poly-pitch scales from 250 nm to 190 nm.

Keywords

MOS integrated circuits; dielectric materials; driver circuits; PMOS drive current; compressively stressed liners; gate dielectrics; mobility advantage; poly-pitch scaling characteristics; stress dependence; CMOS process; Compressive stress; Degradation; Dielectric devices; Dielectric substrates; Fabrication; Leakage current; MOS devices; Scalability; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-03-1

Type

conf

DOI

10.1109/VLSIT.2007.4339753

Filename

4339753