DocumentCode
3485860
Title
Concurrent fault and design error simulation in interactive simulation automation system
Author
Hur, Youngmin ; Shaikh, Saghir ; Goldenberg, S. ; Kacprzak, D. ; Szygenda, Stephen A.
Author_Institution
Quickturn Syst. Inc., Mountain View, CA, USA
fYear
1997
fDate
7-9 Apr 1997
Firstpage
168
Lastpage
176
Abstract
This paper provides efficient design verification methodologies based on concurrent simulation technique which is implemented in the interactive simulation automation system (ISAS). Concurrent simulation is not a new technique, however, the ISAS exploits many parallelisms during the simulation procedure and applies it to three different types of simulation: concurrent (C_sim), distributed concurrent (Dc_sim), and concurrent-concurrent (CON2FERS). ISAS automates the simulation procedure with a graphic user interface and handles not only fault models, but also design error models. It generates fault and design error coverage metrics for the user. This paper provides a description of three types of concurrent simulators with performance results
Keywords
digital simulation; logic CAD; logic testing; ISAS; concurrent; design error coverage metrics; design verification; distributed concurrent; fault models; graphic user interface; interactive simulation; interactive simulation automation system; simulation procedure; Acceleration; Analytical models; Circuit faults; Circuit simulation; Design automation; Design methodology; Digital circuits; Graphics; Instruction sets; Logic design;
fLanguage
English
Publisher
ieee
Conference_Titel
Simulation Symposium, 1997. Proceedings., 30th Annual
Conference_Location
Atlanta, GA
ISSN
1080-241X
Print_ISBN
0-8186-7934-4
Type
conf
DOI
10.1109/SIMSYM.1997.586527
Filename
586527
Link To Document