Title :
Novel domino logic designs
Author :
Haniotakis, Th ; Tsiatouhas, Y. ; Arapoyanni, A.
Author_Institution :
ISD SA, Athens, Greece
Abstract :
Simple to implement, low cost designs in CMOS-domino logic are presented. Novel designs for the two basic gates in domino logic, the AND gate and the OR gate, are presented. These designs need less silicon area and have better performance compared to the standard domino logic designs, while they attain a smaller distribution of the clock signal
Keywords :
CMOS logic circuits; integrated circuit design; logic design; logic gates; AND gate; CMOS-domino logic; OR gate; domino logic designs; full domino logic compatible; low cost designs; Buildings; CMOS logic circuits; Capacitance; Clocks; Costs; Informatics; Logic design; Signal design; Signal processing; Variable structure systems;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.812261
