Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory

A novel multi-level charge trap flash memory with band engineering concept on the trap layer is firstly demonstrated. The engineered band structure, Si₃N₄/Al₂O₃/Si₃N₄ (NAN) was adopted as a trap layer in place of single Si₃N₄ layer in TANOS structure (Y. Shin et al., 2005). Compared to the reference structure of single Si₃N₄ trap layer, charge trap flash memory based on NAN trap layer shows larger memory window (~10 V), which is ideal for multi-level application. In addition, highly reliable operation is obtained due to lower program/erase voltages, superior endurance, and smaller room/high temperature pre-/post-cycling charge loss (DeltaVth <0.5 V).