Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory

Author

Huo, Zongliang ; Yang, JunKyu ; Lim, SeungHyun ; Baik, SeungJae ; Lee, Juyul ; Han, Jeonghee ; Yeo, In-Seok ; Chung, U-in ; Moon, Joo Tae ; Ryu, Byung

Author_Institution

Samsung Electron. Co., LTD., Yongin

fYear

2007

fDate

12-14 June 2007

Firstpage

138

Lastpage

139

Abstract

A novel multi-level charge trap flash memory with band engineering concept on the trap layer is firstly demonstrated. The engineered band structure, Si₃N₄/Al₂O₃/Si₃N₄ (NAN) was adopted as a trap layer in place of single Si₃N₄ layer in TANOS structure (Y. Shin et al., 2005). Compared to the reference structure of single Si₃N₄ trap layer, charge trap flash memory based on NAN trap layer shows larger memory window (~10 V), which is ideal for multi-level application. In addition, highly reliable operation is obtained due to lower program/erase voltages, superior endurance, and smaller room/high temperature pre-/post-cycling charge loss (DeltaVth <0.5 V).

Keywords

aluminium compounds; flash memories; nitrogen compounds; oxygen compounds; silicon compounds; NAN trap layer; Si₃N₄-Al₂O₃-Si₃N₄; TANOS structure; band engineering; multilevel charge trap flash memory; Aluminum oxide; Degradation; Electron traps; Flash memory; Leakage current; Low voltage; Reliability engineering; Silicon compounds; Temperature; Tunneling; Charge Trap Flash (CTF); Multi-Level Cell (MLC); TANOS;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-03-1

Type

conf

DOI

10.1109/VLSIT.2007.4339758

Filename

4339758