DocumentCode
3485920
Title
A new high-performance CMOS-compatible reduced-area bipolar transistor
Author
Emons, C.H.H. ; Hurloc, G.A.M. ; Pijpers, H.E.J. ; Peter, M.S. ; Koster, R. ; Slotboom, J.W.
Author_Institution
Philips Res. Lab., Eindhoven, Netherlands
fYear
1997
fDate
28-30 Sep 1997
Firstpage
44
Lastpage
47
Abstract
A CMOS-compatible single-poly bipolar transistor with implanted collector and minimised emitter-collector distance has been fabricated and characterised. This new concept features good transistor performance with high fT´s (22 GHz) and extremely low collector-substrate capacitances (5 fF) without the use of deep trench-isolation
Keywords
bipolar transistors; ion implantation; 22 GHz; 5 fF; CMOS-compatible single-poly bipolar transistor; collector-substrate capacitance; cut-off frequency; emitter-collector distance; implanted collector; minimum area; BiCMOS integrated circuits; Bipolar transistors; CMOS technology; Capacitance; Contacts; Epitaxial growth; Implants; Isolation technology; Laboratories; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Bipolar/BiCMOS Circuits and Technology Meeting, 1997. Proceedings of the
Conference_Location
Minneapolis, MN
ISSN
1088-9299
Print_ISBN
0-7803-3916-9
Type
conf
DOI
10.1109/BIPOL.1997.647352
Filename
647352
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