Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme

Author

Harris, H. Rusty ; Kalra, Pankaj ; Majhi, Prashant ; Hussain, Muhammed ; Kelly, David ; Oh, Jungwoo ; He, Dawei ; Smith, Casey ; Barnett, Joel ; Kirsch, Paul D. ; Gebara, Gabriel ; Jur, Jess ; Lichtenwalner, Daniel ; Lubow, Abigail ; Ma, T.P. ; Sung, Guan

Author_Institution

SEMATECH, Austin

fYear

2007

fDate

12-14 June 2007

Firstpage

154

Lastpage

155

Abstract

Using strained SiGe on Si, the threshold voltage of high k PMOS devices is reduced by as much as 300 mV. The 80 nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La₂O₃ capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high kappa and metal gates for 32 nm node and beyond.

Keywords

CMOS integrated circuits; MOS integrated circuits; annealing; silicon compounds; DIBL; GIDL; NMOS; SiGe; dual channel CMOS integration; high k PMOS devices; size 32 nm; size 80 nm; standard activation anneal temperature; threshold voltage; Annealing; Capacitive sensors; Germanium silicon alloys; MOS devices; Photonic band gap; Silicon germanium; Strain control; Threshold voltage; Uniaxial strain; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-03-1

Type

conf

DOI

10.1109/VLSIT.2007.4339763

Filename

4339763