CMOS compatible 250 V lateral insulated base transistors

The performance of various insulated base transistors implemented with a digital CMOS compatible high-voltage integrated circuit process was demonstrated. Design modifications in the lateral insulated base transistor (LIBT) structures have been proposed, and the performance of the improved LIBTs has been compared with that of a conventional LIBT structure. These modifications are based on the effective use of charge-controlled n⁺ buried layers to improve the on-state capability of the device. Four different types of LIBT structures have been fabricated and tested. The experimental analysis of the CMOS-compatible LIBTs discussed shows that the n⁺ buried layer placed under the p well plays a crucial role in improving the device performance. The improved LIBT structure with n⁺ buried layers incorporated near the collector and the p well regions shows the best characteristics with high voltage blocking capability, low specific on-resistance, and a low turn-off delay. A specific on-resistance of 0.016 Ω-cm² and a turn-off delay of 90 ns were obtained in the improved LIBT structure, which can withstand up to 250 V