Title :
Challenges at 45nm and beyond
Author :
Bailey, Dan ; Soenen, Eric ; Gupta, Puneet ; Villarrubia, Paul ; Sang Dhong
Author_Institution :
Advanced Micro Devices, Inc., Austin, TX, USA
Abstract :
Design at 45nm technologies and below is a risky proposition because of the many design challenges involved: variability, leakage, verification complexity, poor analog device performance, etc. In this panel, experienced designers coming from different backgrounds talk about how they have overcome some of the design and CAD challenges in 45nm, what CAD challenges still exist and how the CAD community can help.
Keywords :
CMOS technology; Circuit simulation; Costs; DH-HEMTs; Design automation; Environmental economics; Moore´s Law; Physics; Process design; System-on-a-chip;
Conference_Titel :
Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
978-1-4244-2819-9
Electronic_ISBN :
1092-3152
DOI :
10.1109/ICCAD.2008.4681538
