Improved Cell Performance for sub-50 nm DRAM with Manufacturable Bulk FinFET Structure

Author

Lee, Deok-Hyung ; Lee, Sun-Ghil ; Yoo, Jong Ryeol ; Buh, Gyoung-Ho ; Yon, Guk Hyon ; Shin, Dong-Woon ; Lee, Dong Kyu ; Byun, Hyun-Sook ; Jung, In Soo ; Park, Tai-Su ; Shin, Yu Gyun ; Choi, Siyoung ; Chung, U-in ; Moon, Joo-Tae ; Ryu, Byung-Il

Author_Institution

Samsung Electron. Co. Ltd., Gyunggi-Do

fYear

2007

fDate

12-14 June 2007

Firstpage

164

Lastpage

165

Abstract

FinFET, the milestone for sub-50 nm DRAM cell transistor has been successfully demonstrated by a unique fabricating method with novel concept. We obtained a core solution of front-end-of-line process and structure, focusing on short channel behavior, off-state leakage, and saturation current. We have developed the scheme that is able to suppress off-state leakage current below 1 fA/cell with p⁺ poly-Si gate. We have also examined mobility and parasitic engineering techniques to maximize the cell performance (DeltaIon > 48 %). In conclusion, we propose the effective guideline for highly manufacturable FinFET for DRAM application at the sub-50 nm node.

Keywords

DRAM chips; MOSFET; leakage currents; DRAM; bulk finFET structure; fabricating method; front-end-of-line process; mobility; off-state leakage; parasitic engineering techniques; saturation current; short channel behavior; Doping; Fabrication; FinFETs; Guidelines; Leakage current; Manufacturing; Moon; Random access memory; Research and development; Semiconductor device manufacture;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 2007 IEEE Symposium on

Conference_Location

Kyoto

Print_ISBN

978-4-900784-03-1

Type

conf

DOI

10.1109/VLSIT.2007.4339767

Filename

4339767