A novel latch design technique for high speed GaAs circuits

Author

Nooshabadi, Saeid ; Montiel-Nelson, J.A. ; Eshraghian, K.

Author_Institution

Sch. of Electr. Eng., Tasmania Univ., Hobart, Tas., Australia

Volume

1

fYear

1999

fDate

1999

Firstpage

331

Abstract

A GaAs latch design suitable for dynamic logic families is presented. This novel concept is compared with other common GaAs logic circuits in terms of device count, area, clock rate and power consumption. The results demonstrate that the Single Phase Latch (SPL) achieves a throughput 5.7 greater than other dynamic latches while driving twice the capacitive load. It is the simplest, the fastest and consumes less power than other reported dynamic latch structures

Keywords

III-V semiconductors; MESFET integrated circuits; direct coupled FET logic; field effect logic circuits; flip-flops; gallium arsenide; high-speed integrated circuits; integrated circuit design; logic design; DCFL; GaAs; GaAs logic circuits; LFSR design; capacitive load; chip area; clock rate; device count; dynamic domino logics; dynamic latches; dynamic logic families; high speed GaAs circuits; latch design technique; linear feedback shift register; power consumption; single phase latch; Australia; Clocks; Energy consumption; Frequency; Gallium arsenide; Latches; Logic circuits; Logic design; Microelectronics; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.812290

Filename

812290