Title :
Simulation-based sequential equivalence checking of RTL VHDL
Author :
Corno, Fulvio ; Reorda, M. Sonza ; Squillero, Giovunni
Author_Institution :
Dipt. di Autom. e Inf., Politecnico di Torino, Italy
Abstract :
This paper presents a novel approach to equivalence verification of RT-level descriptions. The proposed approach sacrifices exactness in favor of applicability: it is not always able to produce an answer, but it is able to check sequential equivalence of large systems. Furthermore, being based on commercial VHDL tools, it does not have arbitrary limitations in the syntax of the descriptions
Keywords :
circuit simulation; formal verification; hardware description languages; high level synthesis; RAVE; RT-level descriptions; RTL VHDL; commercial VHDL tools; equivalence verification; sequential equivalence checking; simulation-based equivalence checking; Algorithm design and analysis; Circuit simulation; Design automation; Design optimization; Formal verification; Genetic algorithms; Hardware design languages; Mathematical model; Stress; Testing;
Conference_Titel :
Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
Conference_Location :
Pafos
Print_ISBN :
0-7803-5682-9
DOI :
10.1109/ICECS.1999.812295
