3486144

J-R: Are Design Tools and Methodologies Measuring up to the Challenges of the DFM Era?

Odanaka ; Rios, Rafael ; Kumashiro, S. ; Bhavnagarwala, A. ; Hane, M. ; Zhang, Kai ; Masuda, Hiroji ; Lee, Sang-Won ; Radens, Carl ; Amerasekera, A. ; Farrell, Jay A. ; Yoshimura, Hiroyuki

Osaka University

2007

12-14 June 2007

150

150

Crosstalk; Design for manufacture; Design methodology; Etching; Instruments; Large scale integration; National electric code; Predictive models; Timing; Very large scale integration;

English

ieee

VLSI Technology, 2007 IEEE Symposium on

Kyoto, Japan

978-4-900784-03-1

conf

10.1109/VLSIT.2007.4339771

4339771