Real-time FPGA architecture of modified Stable Euler-Number algorithm for image binarization

The stable Euler-Number based image binarization gives excellent visual results for video frames containing high amount of image noise. Being computationally expensive, its implementations are limited to general purpose processors for the most cost-effective solution or in application specific integrated circuits for maximum performance. This paper proposes a modified stable Euler-number based algorithm for image binarization and its real-time hardware implementation in a field programmable gate array with a pipelined architecture. The end result is a design that out-performs known software implementations while keeping the amount of noisy pixels introduced during the binarization process to a minimum. The hardware implementation results show that the proposed architecture gives accurate results compared to the software implementation.