A low-complexity 2D discrete cosine transform processor for multimedia applications

Author

Fanucci, L. ; Saletti, R. ; Vavala, F.

Author_Institution

Centro di Studio per Metodi e Dispositivi per Radiotransmissioni, Nat. Res. Council, Pisa, Italy

Volume

1

fYear

1999

fDate

1999

Firstpage

449

Abstract

This paper describes the project of a processor for the calculation of the direct/inverse two-dimensional discrete cosine transform to be employed in videoconference applications. This processor makes use of the separability technique as calculation method and of an architecture based on distributed arithmetic, in which multipliers are replaced by accumulation-and-shift blocks. The processor was implemented on the AMS 0.8 μm technology with semi-custom approach in order to realize an IP macro-cell to be integrated in multimedia ICs. It features a very low-complexity (15 kgates) for an overall area of 33 mm² and a maximum frequency of 36 MHz. Besides, the processor is fully compliant with accuracy specifications in H.263 recommendation

Keywords

discrete cosine transforms; distributed arithmetic; multimedia communication; teleconferencing; 0.8 micron; 2D discrete cosine transform processor; 36 MHz; AMS; H.263 recommendation; IP macro-cell; accumulation-and-shift blocks; accuracy specifications; calculation method; direct/inverse two-dimensional discrete cosine transform; distributed arithmetic; multimedia applications; semi-custom approach; separability technique; videoconference applications; Arithmetic; Compression algorithms; Computer architecture; Councils; Discrete cosine transforms; Electronic mail; Frequency; Telecommunications; Video compression; Videoconference;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on

Conference_Location

Pafos

Print_ISBN

0-7803-5682-9

Type

conf

DOI

10.1109/ICECS.1999.812319

Filename

812319