• DocumentCode
    348640
  • Title

    The fat Clos ATM switch

  • Author

    Veglis, A.A. ; Pombortsis, A.S.

  • Author_Institution
    Comput. Lab., Aristotelian Univ. of Thessaloniki, Greece
  • Volume
    1
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    469
  • Abstract
    This paper studies a new ATM architecture based on the implementation of channel grouping technique in the widely used Clos switch architecture. Channel grouping is the technique of allocating more than one output port to each output address
  • Keywords
    B-ISDN; asynchronous transfer mode; packet switching; ATM architecture; channel grouping technique; fat Clos ATM switch; output address; output port; switch architecture; Asynchronous transfer mode; Buffer storage; Computer architecture; Electronic mail; Fabrics; Informatics; Packet switching; Routing; Switches; Throughput;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on
  • Conference_Location
    Pafos
  • Print_ISBN
    0-7803-5682-9
  • Type

    conf

  • DOI
    10.1109/ICECS.1999.812324
  • Filename
    812324
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=348640