Accurate energy breakeven time estimation for run-time power gating

Author

Xu, Hao ; Jone, Wen-Ben ; Vemuri, Ranga

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Cincinnati, Cincinnati, OH

fYear

2008

fDate

10-13 Nov. 2008

Firstpage

161

Lastpage

168

Abstract

Run-time Power Gating (RTPG) is a recent technique, which aims at aggressively reducing leakage power consumption. Energy breakeven time (EBT), or equivalent sleep time has been proposed as a critical figure of merit of RTPG. Our research introduces the definition of average EBT in a run-time environment. We develop a method to estimate the average EBT for any given circuit block, considering the impact of circuit states. HSPICE simulation results on ISCAS85 benchmark circuits show that the average EBT model has on the average 1.8% error. The CAD tool implemented based on the model can perform fast estimations with a speedup of 3000times over HSPICE.

Keywords

MOSFET circuits; SPICE; benchmark testing; circuit CAD; circuit simulation; leakage currents; logic gates; CAD; HSPICE simulation; ISCAS85 benchmark circuits; MOSFET; NAND gate; NMOS; circuit block; energy breakeven time; equivalent sleep time; leakage power consumption; run-time power gating; Circuit simulation; Energy consumption; Gate leakage; Leakage current; MOSFET circuits; Power MOSFET; Power generation; Runtime environment; State estimation; Subthreshold current;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on

Conference_Location

San Jose, CA

ISSN

1092-3152

Print_ISBN

978-1-4244-2819-9

Electronic_ISBN

1092-3152

Type

conf

DOI

10.1109/ICCAD.2008.4681568

Filename

4681568