An efficient physical coding sublayer for PCI express in 65nm CMOS

An efficient Physical Coding Sublayer operating at 500MHz has been implemented based on 65 nm CMOS process for PCI Express 2.0, which was integrated into PHY with physical media attachment layer. Two methods of 8b10b codec were compared in area and dynamic power consumption. A reset controller for initialization, elastic buffer for clock compensation and built-in-self-test circuit were employed. The circuit was synthesized at the speed of 500MHz in SS with an area of about 5500 μm² and the dynamic power consumption of 2.74 mW operating in FF.