A novel trench planarization technique using polysilicon refill, polysilicon oxidation, and oxide etchback

Summary form only given. A trench planarization technique is reported which uses polysilicon refill and sequential polysilicon oxidation and oxide etchback processes. Silicon trenches with varying trench depths (1-10 μm) and trench aspect ratios were successfully planarized using this technique. The process uniformity across 4 in. dia. silicon wafers was excellent with MOS gate yields in excess of 95%. Trench capacitors were fabricated and tested for MOS gate interface characteristics and reliability. Trench power MOSFETs were fabricated using a conventional two-step RIE (reactive ion etching) process as well as the proposed technique. It was found that the proposed technique resulted in significant improvements in gate yield and process uniformity, and is easily adaptable in a manufacturing environment for fabricating high-density trench-based active devices, isolation structures, and interconnections