Mapping to reduce contention in multiprocessor architectures

Author

Schwiebert, Loren ; Jayasimha, D.N.

Author_Institution

Dept. of Comput. & Inf. Sci., Ohio State Univ., Columbus, OH, USA

fYear

1993

fDate

13-16 Apr 1993

Firstpage

248

Lastpage

253

Abstract

Reducing communication overhead has been widely recognized as a requirement for achieving efficient mappings which substantially reduce the execution time of parallel algorithms. This paper presents an iterative heuristic for static mapping of parallel algorithms to architectures. Special attention is given to measuring and reducing channel contention. Experimental results are used to show the effects of channel contention for packet-switched networks and the improvement realized by the authors´ heuristic. They also present preliminary results for wormhole-routed networks

Keywords

parallel algorithms; parallel architectures; performance evaluation; resource allocation; channel contention; communication overhead reduction; execution time; iterative heuristic; mappings; multiprocessor architectures; packet-switched networks; parallel algorithms; static mapping; wormhole-routed networks; Computational Intelligence Society; Computational modeling; Computer architecture; Concurrent computing; Information science; Network topology; Parallel algorithms; Parallel architectures; Processor scheduling; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel Processing Symposium, 1993., Proceedings of Seventh International

Conference_Location

Newport, CA

Print_ISBN

0-8186-3442-1

Type

conf

DOI

10.1109/IPPS.1993.262889

Filename

262889