Title :
High resolution and frame rate image signal processor array design for 3-D imager
Author :
Chang-Hsin Cheng ; Hsien-Ching Hsieh ; Tso-Yi Fan ; Wei-Xiang Tang ; Chung-Kai Liu ; Po-Han Huang
Author_Institution :
Inf. & Commun. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan
Abstract :
This paper presents a high resolution and frame rate image signal processor (ISP) array design for three-dimensional (3-D) imager. Based on the through-silicon via (TSV) technology, the short connections of the 3-D integrated circuit (IC) can improve the performance and density. Hence, the 3-D imager is the best solution for high throughput image capture or video recorder applications. The proposed ISP array is based on high resolution CMOS image sensor (CIS) and analog-to-digital converter (ADC) array to achieve three mega pixels (2048×1536) at 100 frames per second in 3-D imager. The architectural simulation results show the proposed design costs area 9000× 7000 μm2, average power 0.79 W and throughput 6.93 bps to verify the feasibility of high resolution and frame rate application for 3-D imager.
Keywords :
CMOS image sensors; analogue-digital conversion; image resolution; three-dimensional integrated circuits; 3D IC; 3D imager; 3D integrated circuit; ADC array; CIS; ISP array design; TSV technology; analog-to-digital converter array; frame rate image signal processor array design; high-resolution CMOS image sensor; high-resolution image signal processor array design; high-throughput image capture; three-dimensional imager; through-silicon via technology; video recorder application; Arrays; Bridge circuits; Image resolution; Integrated circuits; Switching circuits; Throughput; 3-D imager; ISP array; frame rate; high resolution;
Conference_Titel :
Intelligent Signal Processing and Communications Systems (ISPACS), 2012 International Symposium on
Conference_Location :
New Taipei
Print_ISBN :
978-1-4673-5083-9
Electronic_ISBN :
978-1-4673-5081-5
DOI :
10.1109/ISPACS.2012.6473588
