DocumentCode :
3487503
Title :
Layout decomposition for double patterning lithography
Author :
Kahng, Andrew B. ; Park, Chul-Hong ; Xu, Xu ; Yao, Hailong
Author_Institution :
CSE Dept., UC San Diego, San Diego, CA
fYear :
2008
fDate :
10-13 Nov. 2008
Firstpage :
465
Lastpage :
472
Abstract :
In double patterning lithography (DPL) layout decomposition for 45 nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum coloring spacing [11, 9, 5]. However, there exist pattern configurations for which pattern features separated by less than the minimum color spacing cannot be assigned different colors. In such cases, DPL requires that a layout feature be split into two parts. We address this problem using a layout decomposition algorithm that includes graph construction, conflict cycle detection, and node splitting processes. We evaluate our technique on both real-world and artificially generated test cases in 45 nm technology. Experimental results show that our proposed layout decomposition method effectively decomposes given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design rule violations in the final decomposed layout.
Keywords :
decomposition; lithography; double patterning lithography; graph construction; layout decomposition; layout decomposition algorithm; maximized overlap margin; minimum coloring spacing; size 45 nm; Circuits; Costs; Etching; Lithography; Optical materials; Page description languages; Permission; Production; Resists; Ultraviolet sources;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
ISSN :
1092-3152
Print_ISBN :
978-1-4244-2819-9
Electronic_ISBN :
1092-3152
Type :
conf
DOI :
10.1109/ICCAD.2008.4681616
Filename :
4681616
Link To Document :
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