• DocumentCode
    3487642
  • Title

    Obstacle-avoiding rectilinear Steiner tree construction

  • Author

    Li, Liang ; Young, Evangeline F Y

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, Hong Kong
  • fYear
    2008
  • fDate
    10-13 Nov. 2008
  • Firstpage
    523
  • Lastpage
    528
  • Abstract
    In todaypsilas VLSI designs, there can be many blockages in a routing region. The obstacle-avoiding rectilinear Steiner minimum tree (OARSMT) problem has become an important problem in the physical design stage of VLSI circuits. This problem has attracted a lot of attentions in research and several approaches have been proposed to solve this problem effectively. In this paper, we will present a heuristic maze routing based approach to solve this OARSMT problem. It is commonly believed that maze routing based approaches can only handle small scale problems and there is a lack of an effective multi-terminal variant to handle multi-pin nets in practice. We will show in this paper that maze routing based approaches can also handle large scale OARSMT problems effectively. Our approach is based on the searching process as in maze routing and can handle multi-pin nets very well in both solution quality, running time and memory space usage. We have compared our results with those of the previous works and can show that we can out-perform the best previous results on this problem [15] by giving an OARSMT with 2.01% less wire length on average and can make a 27.04% improvement in wire length in comparison with a lower bound of the optimal solution on average, while the running times are all very short and comparable to those in [15]. Besides, due to the flexibility of maze routing, we can handle different kinds of obstacles with different convex or concave rectilinear shapes directly without a need to partition each blockage into a set of rectangular sub-blockages, which will increase the size of the problem.
  • Keywords
    VLSI; circuit layout CAD; integrated circuit layout; network routing; trees (mathematics); VLSI circuits; heuristic maze routing; multipin nets; obstacle-avoiding rectilinear Steiner minimum tree; Ant colony optimization; Circuits; Computer science; Large-scale systems; Pins; Routing; Shape; Steiner trees; Very large scale integration; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    978-1-4244-2819-9
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2008.4681625
  • Filename
    4681625