DocumentCode
3487662
Title
Low power CMOS LNA design optimization techniques
Author
Wu, Xiushan ; Shen, Xiaoyan ; Wang, Zhigong ; Li, Qing
Author_Institution
Coll. of Electr. & Mech. Eng., China Jiliang Univ., Hangzhou
fYear
2008
fDate
16-20 Dec. 2008
Firstpage
1
Lastpage
4
Abstract
Based on the noise parameter expressions of the proposed CMOS LNA topology, the design principles, advantages, and limitations of the power-constrained simultaneous noise and input matching technique are discussed. As a demonstration for the proposed design principle, a 433 MHz low-power CMOS LNA is implemented in SMIC´s 0.18 mum CMOS technology. Measured results show a good agreement with the proposed design principle and theoretical analysis.
Keywords
CMOS integrated circuits; circuit optimisation; integrated circuit design; low noise amplifiers; network topology; CMOS LNA design optimization techniques; CMOS LNA topology; frequency 433 MHz; input matching technique; noise parameter expressions; power-constrained simultaneous noise; CMOS technology; Circuit noise; Design optimization; Frequency; Impedance matching; MOSFETs; Noise figure; Optimized production technology; Parasitic capacitance; Power dissipation;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave Conference, 2008. APMC 2008. Asia-Pacific
Conference_Location
Macau
Print_ISBN
978-1-4244-2641-6
Electronic_ISBN
978-1-4244-2642-3
Type
conf
DOI
10.1109/APMC.2008.4958348
Filename
4958348
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