Low-voltage multi-level flash memory: determination of minimum spacing between multi-levels [CMOS]

Author

Chi, Min-Hwa ; Bergemont, Albert

Author_Institution

Adv. Technol. Group, Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

1996

fDate

26-28 Nov 1996

Firstpage

1

Lastpage

5

Abstract

This paper reports that cell reliability issues (e.g. V_T spread, program disturb, read disturb, subthreshold leakage current, and charge retention), read scheme, and cell structures are the factors for minimizing V_T spacing for multi-level storage in flash memory. A 2T cell structure is proposed for wider V_T window, high speed read, and smaller V_T spacing in order to store more V_T levels than 1T cell

Keywords

CMOS memory circuits; EPROM; cellular arrays; integrated circuit reliability; leakage currents; 2T cell structure; CMOS; V_T spread; cell reliability issues; cell structures; charge retention; low-voltage multi-level flash memory; minimum spacing; program disturb; read disturb; read scheme; subthreshold leakage current; CMOS technology; Charge carrier processes; Flash memory; Linear programming; Linearity; Low voltage; Nonvolatile memory; Secondary generated hot electron injection; Semiconductor device reliability; Subthreshold current;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 1996. ICSE '96. Proceedings., 1996 IEEE International Conference on

Conference_Location

Penang

Print_ISBN

0-7803-3388-8

Type

conf

DOI

10.1109/SMELEC.1996.616439

Filename

616439