Title :
Low-voltage multi-level flash memory: determination of minimum spacing between multi-levels [CMOS]
Author :
Chi, Min-Hwa ; Bergemont, Albert
Author_Institution :
Adv. Technol. Group, Nat. Semicond. Corp., Santa Clara, CA, USA
Abstract :
This paper reports that cell reliability issues (e.g. VT spread, program disturb, read disturb, subthreshold leakage current, and charge retention), read scheme, and cell structures are the factors for minimizing VT spacing for multi-level storage in flash memory. A 2T cell structure is proposed for wider VT window, high speed read, and smaller VT spacing in order to store more VT levels than 1T cell
Keywords :
CMOS memory circuits; EPROM; cellular arrays; integrated circuit reliability; leakage currents; 2T cell structure; CMOS; VT spread; cell reliability issues; cell structures; charge retention; low-voltage multi-level flash memory; minimum spacing; program disturb; read disturb; read scheme; subthreshold leakage current; CMOS technology; Charge carrier processes; Flash memory; Linear programming; Linearity; Low voltage; Nonvolatile memory; Secondary generated hot electron injection; Semiconductor device reliability; Subthreshold current;
Conference_Titel :
Semiconductor Electronics, 1996. ICSE '96. Proceedings., 1996 IEEE International Conference on
Conference_Location :
Penang
Print_ISBN :
0-7803-3388-8
DOI :
10.1109/SMELEC.1996.616439
