CMOS latchup characterization for LDMOS/LIGBT power integrated circuits

Author

Chan, Wilson W T ; Sin, Johnny K O ; Mok, Philip K T ; Wong, S. Simon

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Clear Water Bay, Hong Kong

fYear

1996

fDate

26-28 Nov 1996

Firstpage

15

Lastpage

18

Abstract

This paper presents a unique characterization technique for CMOS latchup in power integrated circuits. To this purpose, test structures are designed and implemented using a 2-μm twin-well CMOS/LDMOS/LIGBT high voltage process. Lumped element models are used to study the latching mechanism. Crosstalk between LDMOS and CMOS as well as between LIGBT and CMOS is investigated. It is shown that great care should be taken when designing power integrated circuits since CMOS latchup is initiated even at low operating current of the power devices

Keywords

CMOS analogue integrated circuits; insulated gate bipolar transistors; integrated circuit modelling; integrated circuit testing; power integrated circuits; 2 micron; CMOS latchup characterization; LDMOS/LIGBT power integrated circuits; latching mechanism; lumped element models; operating current; test structures; twin-well CMOS/LDMOS/LIGBT high voltage process; CMOS process; CMOS technology; Circuit testing; Diodes; Power integrated circuits; Power transistors; Steady-state; Substrates; Thyristors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Electronics, 1996. ICSE '96. Proceedings., 1996 IEEE International Conference on

Conference_Location

Penang

Print_ISBN

0-7803-3388-8

Type

conf

DOI

10.1109/SMELEC.1996.616442

Filename

616442