DocumentCode
3488721
Title
Cache Preemption Related Delay Accounting via Static Analysis and Functional Simulation
Author
Starke, Renan Augusto ; de Oliveira, Romulo S.
Author_Institution
DAS-CTC, Univ. Fed. de Santa Catarina, Florianopolis, Brazil
fYear
2012
fDate
5-7 Nov. 2012
Firstpage
149
Lastpage
152
Abstract
Cache memory related preemption delay causes large variations of the task execution time and tools that perform WCET static code analysis usually do not consider this behavior. The additional cache delays are usually solved by cache partitioning between tasks or they are incorporated in the schedulability analysis equations. This paper estimates the cache preemption delay of a task in two steps: task static analysis for the instruction cache and functional simulation for the data cache. Both steps are used to track the memory references. After that, we estimate which cache blocks may actually cause additional cache faults in a preemption. Due to the use of functional simulation, the calculated cache preemption delay is not the worst case, but this technique does not rely on WCET tools nor the real hardware. After this analysis, we determine the cost of preemption at each point of the program more accurately.
Keywords
cache storage; delays; instruction sets; program diagnostics; scheduling; WCET static code analysis; cache block; cache fault; cache memory related preemption delay; cache partitioning; cache preemption related delay accounting; data cache; functional simulation; instruction cache; memory reference tracking; schedulability analysis equation; task execution time; task static analysis; Analytical models; Delay; Electronic mail; Mathematical model; Random access memory; Real-time systems; Software;
fLanguage
English
Publisher
ieee
Conference_Titel
Computing System Engineering (SBESC), 2012 Brazilian Symposium on
Conference_Location
Natal
ISSN
2324-7886
Print_ISBN
978-1-4673-5747-0
Type
conf
DOI
10.1109/SBESC.2012.36
Filename
6473652
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