DocumentCode :
3488810
Title :
A Methodology to Adapt Data Path Architectures to a MIPS-1 Model
Author :
Casillo, L.A. ; Silva, I.S.
Author_Institution :
Dept. of Exact & Natural Sci., Fed. Rural Univ. of the Semi-Arid, Mossoró, Brazil
fYear :
2012
fDate :
5-7 Nov. 2012
Firstpage :
172
Lastpage :
177
Abstract :
MIPS (Microprocessor without Interlocked Pipeline Stages) is an Instruction Set Architecture used in applications such as computers, routers, game consoles and various embedded systems. Among the advantages of this pattern, it could be cited the variety of free software such as compilers and simulators. This paper shows a methodology required to adapt other architectures to use a MIPS-1 instruction set without significant increase in chip area and power dissipation. This methodology was applied in two case studies, which architectures at different complexity levels data paths will be adapted to a new model.
Keywords :
computer architecture; instruction sets; microprocessor chips; power aware computing; public domain software; ISA; MIPS-1 instruction set architecture; chip area; complexity level data path architectures; free software; microprocessor without interlocked pipeline stages; power dissipation; Clocks; Complexity theory; Computer architecture; Power dissipation; Program processors; Registers; Standards; ISA; MIPS; didactic processors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computing System Engineering (SBESC), 2012 Brazilian Symposium on
Conference_Location :
Natal
ISSN :
2324-7886
Print_ISBN :
978-1-4673-5747-0
Type :
conf
DOI :
10.1109/SBESC.2012.41
Filename :
6473657
Link To Document :
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