Title :
A feasible VLSI engine for soft-input-soft-output for joint source channel codes
Author :
Zezza, Simone ; Masera, Guido ; Nooshabadi, Saeid
Author_Institution :
VLSI Lab., Politec. di Torino, Torino, Italy
Abstract :
This paper proposes for the first time, the very large scale integration (VLSI) architectural techniques for error resilient joint source channel coding (JSCC) of arithmetic codes (AC). When implemented on a 0.13 ¿m standard cells technology running at 340 MHz, achieves a decoding throughput of up to 125 kbit/s, 58 times better than the standard implementation.
Keywords :
UHF integrated circuits; VLSI; arithmetic codes; combined source-channel coding; VLSI engine; arithmetic codes; frequency 340 MHz; joint source channel coding; soft-input-soft-output; very large scale integration architectural techniques; Arithmetic; Channel coding; Computational complexity; Concatenated codes; Cross layer design; Engines; Forward error correction; Iterative decoding; Throughput; Very large scale integration; Joint source channel coding; VLSI; error resilience arithmetic codes; wireless multimedia;
Conference_Titel :
Image Processing (ICIP), 2009 16th IEEE International Conference on
Conference_Location :
Cairo
Print_ISBN :
978-1-4244-5653-6
Electronic_ISBN :
1522-4880
DOI :
10.1109/ICIP.2009.5414132
