Title :
An innovative technique to examine gate oxide anomaly for failure analysis
Author :
Chan, H.G. ; Lit, Y.K.
Author_Institution :
Motorola, Petaling Jaya, Malaysia
Abstract :
A new and innovative technique to examine gate oxide anomaly and particulate within oxide interface for MOS devices whilst preserving the silicon substrate is presented in this paper. This technique incorporates parallel face lapping and a highly selective polysilicon chemical etch to uncover gate oxide without difficulty. Case studies of two types of MOS devices are also presented in this paper
Keywords :
MIS devices; MOS integrated circuits; VLSI; elemental semiconductors; etching; failure analysis; inspection; semiconductor device reliability; silicon; MOS devices; Si; VLSI; failure analysis; gate oxide anomaly; oxide interface particulate; parallel face lapping; polysilicon chemical etch; Aluminum; Chemical vapor deposition; Failure analysis; Hydrogen; Inspection; Lapping; MOS devices; Silicon compounds; Very large scale integration; Wet etching;
Conference_Titel :
Semiconductor Electronics, 1996. ICSE '96. Proceedings., 1996 IEEE International Conference on
Conference_Location :
Penang
Print_ISBN :
0-7803-3388-8
DOI :
10.1109/SMELEC.1996.616445
