Extraction of open-via defects from industrial designs

Author

Ladhar, Aymen ; Masmoudi, Mohamed

Author_Institution

STMicroelectron., Sfax, Tunisia

fYear

2009

fDate

6-8 Nov. 2009

Firstpage

1

Lastpage

6

Abstract

As shown by previous studies, shorts and opens should be considered as the predominant cause of failures in CMOS circuits. Fault models and tools targeting the extraction of these defects focused only on the bridging faults in order to generate test patterns or to use this information for a precise fault diagnosis. However, for open defects there is no available commercial tool that performs the extraction of this defect. In this paper, we present a novel algorithm to extract the location of potential open defects caused by defective vias. This information is used to generate a subnet list containing the name of disconnected segments by each defective via. Experiments on real industrial designs show the algorithm´s performance. The method proposed in this paper is supported by a design flow implementing existing commercial CAD tools.

Keywords

CMOS integrated circuits; automatic test pattern generation; fault simulation; integrated circuit design; integrated circuit interconnections; integrated circuit testing; CMOS circuits; bridging faults; commercial CAD tools; defective vias; disconnected segments; fault diagnosis; fault models; fault tools; industrial designs; interconnect opens; open defects; open-via defects; subnet list; test pattern generation; Circuit faults; Circuits and systems; Communication industry; Data mining; Design automation; Fault diagnosis; Integrated circuit interconnections; Lithography; Process design; Testing; Defect extraction; Interconnect opens; Open-via defects;

fLanguage

English

Publisher

ieee

Conference_Titel

Signals, Circuits and Systems (SCS), 2009 3rd International Conference on

Conference_Location

Medenine

Print_ISBN

978-1-4244-4397-0

Electronic_ISBN

978-1-4244-4398-7

Type

conf

DOI

10.1109/ICSCS.2009.5414144

Filename

5414144