Metal gate thickness optimization for MuGFET performance improvement

In this paper, we investigate the dependence between the performance of multiple-gate FETs (dasiaMuGFETspsila) and the thickness of their plasma-enhanced-ALD (PE-ALD) TiN gate electrode. We show that very thin PE-ALD-TiN gate electrodes allow improved short channel effect (SCE) control and enhanced performance in n-channel MuGFETs without mobility modification. Based on the electrical characterization of MuGFETs and the physical analysis of their gate stacks, we show that the thickness of the TiN metal gate affects the nature of its reaction with the gate dielectric. This, in return, results into threshold voltage (VT) and gate inversion thickness (Tinv) modifications which can explain performance enhancement in n-FETs without any performance loss in p-FETs.