An investigation on power plane decoupling for high speed multiprocessor boards

New generations of high speed processors are requiring more power. Consequently in order to cope with the high amount of switching currents, efficient decoupling of power planes has become critical for both signal integrity (SI) and EMC. In this paper an investigation has been conducted to find out the effects of decoupling capacitors on SI and EMC. A procedure for optimizing the decoupling capacitors based on the fundamental frequency and harmonic frequencies has been illustrated. The optimized decoupling strategy was then implemented on a dual processor board and the emissions were measured in a semi-anechoic chamber. The authors have tried to find out the effect of the decoupling strategy on both SI and EMI