Author :
Fenouillet-Beranger, C. ; Denorme, S. ; Perreau, P. ; Buj, C. ; Faynot, O. ; Andrieu, F. ; Tosti, L. ; Barnola, S. ; Salvetat, T. ; Garros, X. ; Casse, M. ; Allain, F. ; Loubet, N. ; Pham-Nguyen, L. ; Deloffre, E. ; Gros-Jean, M. ; Beneyton, R. ; Laviron,
Abstract :
In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX thicknesses with or without ground plane (GP). With a simple High-k/Metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well situated for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk shrunk technology in terms of variability and noise. 0.499 mum2 SRAM cell has been characterized with less than 50 pA of standby current/cell and a SNM of 210 mV @ Vdd 1V.
Keywords :
MOSFET; SRAM chips; high-k dielectric thin films; metal-insulator boundaries; semiconductor device noise; silicon-on-insulator; BOX; FDSOI devices; MOSFET; SRAM cell; fully-depleted SOI devices; ground plane conditions; ground plane integration; high-k-metal gate structure; noise; size 32 nm; standby current; Annealing; CMOS technology; Electrostatics; Epitaxial growth; Fabrication; High-K gate dielectrics; MOS devices; Thin film devices; Threshold voltage; Tin;
