A low complexity architecture for complex discrete wavelet transform

This paper presents a low complexity architecture for realization of CDWT for minimal resource environment like FPGA and SoC applications in image processing. The proposed architecture uses parameterization of the coefficients for reduced redundancy in computation. Use of CSD based multipliers along with pipelined CORDIC provided an architecture for efficient implementation in contrained environment along with high speed and efficiency. Low data path length and lower control complexity are other salient features of the architecture presented in the paper. This design was implemented on Xilinx FPGA platform. The operational frequency of the implemented circuit is 47 MHz.