Title :
Fully-depleted accumulation-mode PMOSFET for 0.2 μm SOI technology
Author :
Raynaud, C. ; Pelloie, J.L. ; Faynot, O. ; Dunne, B. ; Hartmann, J.
Author_Institution :
Lab d´´Electron. et de Technol. de l´´Inf., CEA, Centre d´´Etudes Nucleaires de Grenoble, France
Abstract :
SOI technology is a promising candidate for low-voltage low-power applications where both partially and fully depleted devices can be used to fulfil the related requirements. One advantage of fully-depleted devices is that a single N+ gate process can be kept for an advanced CMOS process. We show in this paper that an accumulation-mode fully-depleted PMOSFET using an N+ gate can be optimized for a 0.2 μm SOI CMOS technology
Keywords :
CMOS integrated circuits; MOSFET; integrated circuit technology; silicon-on-insulator; 0.2 micron; LV applications; N+ gate process; SOI CMOS technology; Si; accumulation-mode PMOSFET; fully-depleted PMOSFET; p-channel MOSFET; Aging; CMOS technology; Electric variables; Electron traps; Impact ionization; Length measurement; Lithography; MOSFET circuits; Testing; Threshold voltage;
Conference_Titel :
SOI Conference, 1995. Proceedings., 1995 IEEE International
Conference_Location :
Tucson, AZ
Print_ISBN :
0-7803-2547-8
DOI :
10.1109/SOI.1995.526436
