Latency insertion method for the analysis of steady state on-chip power distribution networks and transient simulation of lossy interconnects

Process scaling has led to a significant growth in the number or devices on a chip. Consequently, the length and density of interconnects has increased dramatically. Tradional matrix-vector product based circuit simulations such as SPICE are not computationally efficient for analysis of large circuit problems. This work demonstrates that latency insertion method (LIM) algorithm can be extended to incorporate frequency dependent behavior of circuit elements in the simulation. This method is applied to the analysis of steady-state on-chip power distribution network. Experimental results show that LIM outperforms the random walk method, especially for circuits with large numbers of nodes. Also,expansion of the LIM algorithm to the treatment of networks with frequency-dependent parameters is presented. The ability of the expanded algorithm to model lossy interconnects is demonstrated.