Title :
Handling zero in diminished-1 modulo 2n + 1 subtraction
Author :
Efstathiou, Costas ; Voyiatzis, Ioannis
Author_Institution :
Dept. of Inf., TEI of Athens, Athens, Greece
Abstract :
In this work efficient architectures of modulo 2n+1 subtractors for diminished-1 operands which can handle zero operand are presented. The proposed subtractors have similar architecture, operate at the same speed and have the same area complexity compared to their corresponding modulo 2n+1 adders for diminished-1 operands. Efficient modulo 2n+1 adder/subtractor architectures for diminished-1 operands, which are welcomed in RNS applications, are also proposed.
Keywords :
adders; computational complexity; digital arithmetic; diminished-1 modulo 2n + 1 subtraction; diminished-1 operands; modulo 2n+1 adders; subtractor architectures; Adders; Circuits and systems; Computer architecture; Concurrent computing; Delay; Digital arithmetic; Informatics;
Conference_Titel :
Signals, Circuits and Systems (SCS), 2009 3rd International Conference on
Conference_Location :
Medenine
Print_ISBN :
978-1-4244-4397-0
Electronic_ISBN :
978-1-4244-4398-7
DOI :
10.1109/ICSCS.2009.5414182
