A novel CMP method for cost-effective bonded SOI wafer fabrication

Author

Lee, B.H. ; Kang, C.J. ; Lee, J.H. ; Yu, S.I. ; Lee, K.-W. ; Park, K.C. ; Shim, T.E.

Author_Institution

Semicond. Res. & Dev. Center, Samsung Electron., Kyungki, South Korea

fYear

1995

fDate

3-5 Oct 1995

Firstpage

60

Lastpage

61

Abstract

The BOnded Silicon On Insulator (BOSOI) has been considered as a promising substitute for bulk silicon technology because of its structural flexibility. However,there are considerable drawbacks if epitaxial etch stopping or localized plasma etching technique is used in the fabrication process because of low throughput and high cost. In order to obtain the ultrathin SOI layer with uniform thickness, this paper describes the cost-effective fabrication method of bonded SOI wafer using the double step CMP method in which the abrasive concentration of slurry is controlled to enhance the polish throughput. In this technique, a low total thickness variation (TTV) wafer is used as a handle wafer and the thickness variation of SOI layer can be easily reduced within a reasonable polishing time if the abrasive concentration of slurry is properly adjusted

Keywords

abrasion; polishing; silicon-on-insulator; wafer bonding; BOSOI; CMP method; abrasive concentration; bonded SOI wafer fabrication; chemical-mechanical polishing; double step method; polish throughput; slurry; total thickness variation; Abrasives; Costs; Etching; Fabrication; Plasma applications; Silicon on insulator technology; Slurries; Thickness control; Throughput; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI Conference, 1995. Proceedings., 1995 IEEE International

Conference_Location

Tucson, AZ

Print_ISBN

0-7803-2547-8

Type

conf

DOI

10.1109/SOI.1995.526460

Filename

526460