Analytical threshold voltage model for short channel n+-p+ double-gate SOI MOSFETs

Previously, we proposed n⁺-p⁺ double-gate SOI MOSFETs, and fabricated this device, and demonstrated high-speed, low-power performance with a gate length L_G of 0.2 μm. In this paper, we have derived a threshold voltage model V_th for short channel devices to predict how far this device can be scaled. Using this model, which agrees with numerical data, we evaluated V_th lowering ΔV_th with decreasing the gate length L_G, and showed that we can design a 0.05 μm-L_G device with ΔV_th of 25 mV and an S-swing of 65 mV/decade