Schematic extraction from layout of microwave multi-layer circuits

As the design getting more complex, a design verification tools is required to ensure quality design. The extraction of L/C from layout is the first step for automatically layout vs. schematic (LVS) check. Computation geometry algorithms are applied to extract capacitors and inductors from layout of multi-layer circuits. The algorithm to generate overall schematic from extracted L/C is also presented. The extracted schematic of layout in published paper show good accuracy of our proposed algorithms.