Optimisation of wirebond interconnects by automated parameter variation

A numerical optimisation strategy for interconnections in electronic packaging is demonstrated. The method is based on a toolbox for the parametric generation of finite- element models of package types such as Chip Scale Package (CSP), Micro Lead Package (MLP) or Ball Grid Array (BGA). The novelty of this work is the combination of this modeling toolbox with an optimisation software for automatic parameter variation. Resulting in a convenient tool to investigate the influence of geometry on the relevant quality characteristics of the device. Users can set the parameters to be varied, the ranges of parameter variation and the number of iterations. The optimisation software automatically generates the parameter sets depending on the number of iterations. The generation of a finite-element model for each parameter set, the meshing and the implementation of the required material properties are also automated by the toolbox. Thereafter, the simulation of the desired load conditions results in quality characteristics such as the maximum mechanical stress for each set. After completion of all iterations, the optimisation software provides a user interface for statistical analysis and graphic visualisation of the results. The wirebond geometry is also included in the toolbox. Influence on maximum mechanical stress and fatigue properties under thermal loads is examined during this study. As an example, the effect of the bonding tool geometry on the locations and the value of the maximum mechanical stress in the wirebond material during thermal shocking is determined. This combination of parametric finite-element model generation and automatic parameter variation represents a powerful tool for design automation in packaging technology and product development. The effects of several geometrical parameters on the thermal and mechanical behaviour of packaging interconnects can be predicted. In a virtual product-development process, time- and cost-intensive prototyping and testin- - g can thus be reduced.