Failure modelling in flexible electronics

The first part of this paper deals with the analysis of layer buckling and delamination of thin him multi-layer structures that are used in flexible display applications. To this end, 250 nm thick indium tin oxide (ITO) layers have been deposited on a 200 mum thick high temperature aromatic polyester substrate (Arylitetrade) with a 3 mum silica-acrylate hybrid hard coat (HC). Typical buckle morphologies are determined from two-point bending experiments, in which buckle widths and heights are measured after straightening of the sample. Finite element simulations have been performed to estimate the corresponding interface properties and compressive strains in the layers, and to illustrate the effect of sample straightening on the buckle geometry. The second part considers the fracture sensitivity analysis of an active matrix Thin Film Transistor (TFT) display containing 512 times 256 pixels, with a typical pixel dimension of 160 times 160 mum. Due to the large scale differences between the display and the TFT patterning a multi-scale modelling framework has been developed, which allows to include realistic material stacks and a detailed pixel geometry. The resulting patterning effect shows an anisotropic behaviour at both the pixel level and the global display level due to the multi-scale approach. Using the Area Release Energy (ARE) method an energy-based failure criterion has been utilised to analyse cohesive failure at several (critical) locations in the pixel geometry. Specifically, the sensitivity to tunnelling cracks in the dielectric layers is regarded, which have been experimentally observed in comparable TFT samples that are subjected to tension. This local failure analysis allows for the identification of critical regions within the pixel geometry, which strongly depend on the location.