Title :
Area/yield trade-offs in scaled CMOS SRAM cell
Author :
Gupta, Vasudha ; Anis, Mohab
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON
Abstract :
A statistical design method, for the SRAM bit-cell, is proposed to ensure a high yield, while meeting the specifications of stability, writability, read speed, leakage and area. Optimal bit-cell designs in the 65 nm, 45 nm and 32 nm technologies are derived. It is demonstrated that memory partitioning and longer transistors enable smaller transistor widths, and a close to 50% scaling of the bit-cell area with technology.
Keywords :
CMOS memory circuits; SRAM chips; integrated circuit yield; logic design; scaling circuits; CMOS SRAM bit-cell design; circuit scaling; integrated circuit yield; memory partitioning; size 32 nm; size 45 nm; size 65 nm; statistical design method; transistor width; Degradation; Design automation; Design methodology; Driver circuits; Fluctuations; Probability; Random access memory; Resource description framework; Stability; Virtual reality; SRAM (Static random access memory); optimization;
Conference_Titel :
Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European
Conference_Location :
Edinburgh
Print_ISBN :
978-1-4244-2361-3
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2008.4681790
