Investigation of BPSG profile and FAB size Cu stud bumping process by modeling and experiment

Flip chip technology is a widely used package for high-performance semiconductor devices. However, flip-chip growth in consumer electronics has been hampered because the technique has to face several challenges and is an expensive processes to implement. Stud-bump bonding (SBB) technology, which is based on wire-bonding technology, has been developed as a solution to lower the cost of the flip-chip process. The major Cu stud bumping process consists of two steps: one is a bonding process, the other is a shearing process after the bonding process is completed. During the Cu stud bumping process, wafer cratering may be induced by the large stress under the bondpad. Cratering means the copper stud comes off and creates a local deformed area in the silicon or dielectric layers at the site of the bond. A couple of factors may be related to the wafer cratering. In this paper, the impact of borophosphosilicate glass (BPSG) profile and size of Cu free air ball (FAB) are thoroughly investigated. Both 2-D and 3-D models are built for the simulations of Cu stud bonding and shearing process. Simulation results show that the smaller FAB induces significant less stress in silicon than the larger FAB case in bonding process. However, this is the opposite in shearing process. Experiments tests are also conducted to formulate different BPSG film profile. Then the ball cratering tests are conducted after Cu stud bumping and solder ball reflow. The experiment results indicate that the BPSG profile does not show any significant impact on Cu-stud related wafer cratering, which agrees with the simulation results.