DocumentCode
3490454
Title
Characteristics of submicrometer LOCOS isolation
Author
Thomas, Jeffrev W. ; Chung, James E. ; Keast, Craig L.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA
fYear
1995
fDate
3-5 Oct 1995
Firstpage
116
Lastpage
117
Abstract
For future VLSI technologies, ensuring acceptable device isolation becomes increasingly important. In this study, fundamental variables for submicrometer LOCOS isolation including the top-layer silicon thickness, the stress-relief-oxide (SRO) thickness, the percent field over-oxidation, and field implant conditions have been explored. How these variables impact the minimum achievable isolation spacing as well as the susceptibility to MOS side-gating is examined
Keywords
MOSFET; isolation technology; oxidation; semiconductor technology; silicon-on-insulator; MOS side-gating; SOI MOSFETs; VLSI technologies; field implant; percent field over-oxidation; stress-relief-oxide thickness; submicrometer LOCOS isolation; top-layer silicon thickness; Computer science; Displays; Implants; Isolation technology; Laboratories; MOSFETs; Oxidation; Silicon; Stress; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference, 1995. Proceedings., 1995 IEEE International
Conference_Location
Tucson, AZ
Print_ISBN
0-7803-2547-8
Type
conf
DOI
10.1109/SOI.1995.526488
Filename
526488
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