Efficient VLSI architecture for bit plane encoder of JPEG 2000

In this paper an optimized architecture of bit plane coder for Embedded Block Coding with Optimal Truncation (EBCOT) algorithm targeting its FPGA implementation is proposed. Although several speed up techniques exist, we present architecture whose performance is improved based on detailed analysis of data path used to obtain context windows. Multiplexer based coding style is adapted to utilize the resources optimally. After place and route on Xilinx XC2VP30 the proposed design operates at 82 MHz which is capable of encoding 720p (HDTV 1280 × 720, 4:2:2) pictures at nearly 44 frames per second. Even though 14 bit planes are used, the implementation results show that the consumption of logic resources in terms of LUTs, slices and flip-flop slices have reduced drastically compared to that of reported designs [1, 2, 3, 4 and 5].