Title :
Dynamic reconfiguration schemes for mega bit BiCMOS SRAMs
Author :
Rayapati, Venkatapathi N. ; Kaminska, Bozena
Author_Institution :
Dept. of Electr. Eng., Ecole Polytech. de Montreal, Que., Canada
Abstract :
In this paper two dynamic reconfiguration schemes are discussed for mega bit BiCMOS SRAMs. These schemes allow the failure detection at the chip level and automatic reconfiguration to fault free memory cells within the chip. BiCMOS SRAM access time improvement of about 35%, chip area of 25%, and chip yield of 10% are achieved respectively, as compared to the conventional methods
Keywords :
BIMOS integrated circuits; SRAM chips; circuit reliability; redundancy; BiCMOS SRAMs; access time improvement; automatic reconfiguration; chip area; chip yield; dynamic reconfiguration schemes; failure detection; fault free memory cells; mega bit; megabit static RAM; BiCMOS integrated circuits; Decoding; Degradation; Electrical fault detection; Energy consumption; Fault detection; Hardware; Random access memory; Redundancy; SRAM chips;
Conference_Titel :
Memory Testing, 1993., Records of the 1993 IEEE International Workshop on
Conference_Location :
San Jose, CA
Print_ISBN :
0-8186-4150-9
DOI :
10.1109/MT.1993.263137
